Time base signals are used extensively in integrated circuits for timing processes, particularly in microprocessors or microcontrollers.
As an example, FIG. 1 very schematically represents the architecture of a microprocessor MP1 comprising a classical time base circuit TBCT1 of the type described in document FR 2 789 501.
The microprocessor comprises a central processing unit or CPU, a program memory MEM, and a data bus DBUS linking the CPU and the memory MEM. The CPU is timed by a primary clock signal H1 supplied by a clock circuit CKGEN comprising a precision oscillator OSC1, such as a quartz oscillator, and a frequency divider PSC (“prescaler”). The oscillator OSC1 delivers a clock signal H0 applied to the divider PSC the output of which delivers the primary clock signal H1.
The time base circuit TBCT1 comprises a programmable countdown counter DCNT timed by the clock signal H1. The countdown counter DCNT is linked to a set point register TBREG at least write accessible by means of the data bus DBUS, in which a time base counting value TBVAL is recorded.
The countdown counter DCNT comprises an output OUTZ that delivers a time base signal TBS having a pulse of determined value (0 or 1) upon each change to zero of the countdown counter DCNT. The pulse of the time base signal TBS is applied to the countdown counter DCNT as a signal RLD (“RELOAD”) for loading-the value TBVAL present in the countdown counter DCNT. Therefore, the countdown counter DCNT automatically loads the value TBVAL at the end of each counting cycle and the time base signal TBS has periodic pulses of period Tb equal to T1*TBVAL, T1 being the period of the clock signal H1.
The signal TBS is applied to an interrupt decoder ITDEC that supplies the CPU with an interrupt signal TBIT at each pulse of the signal TBS. The period of the interrupt signals TBIT is therefore equal to the period Tb of the pulses of the time base signal, if the interrupt signal is not masked.
Various applications of this time base signal may be made.
The CPU can for example be put into an active halt state (“Active Halt Mode”) between two pulses of the time base signal TBS. This active halt mode results in the fact that various current-consuming peripheral circuits are stopped, except for the clock circuit CKGEN and the countdown counter DCNT. The CPU is reactivated when the pulse of the time base signal TBS is emitted.
In addition to the management of an active halt mode, the time base signal TBS also allows a real time clock or timer (not represented) to be managed that is incremented upon each pulse of the signal TBS. The value TBVAL is for example chosen so that the period Tb of the time base signal is equal to one second or to a fraction of a second.
In one known proposed, but rejected design of the microprocessor MP1, the circuit TBCT1 is driven by a secondary oscillator OSC2 delivering a clock signal H2, represented in dotted lines in FIG. 1. In this case, the clock signal H2 is applied to the clock input of the countdown counter DCNT instead of the clock signal H1. This solution is considered in the above-mentioned document FR 2 789 501, but it is not chosen on the grounds that providing the second oscillator OSC2 occupies a considerable surface area of silicon and increases the cost price of the microprocessor.